1. Field of the Invention
The present invention relates to methods and apparatus for testing circuits incorporating memory arrays and more particularly to such methods and apparatus in which a test vector comprising a preselected string of digital data is loaded into the array and resulting strings are read out.
2. Description of the Related Art
Many circuits incorporate an array of memory registers which function as latches for temporarily storing data before and/or after logic operations are formed on the stored data. One such circuit is known as a systolic array. Such a circuit includes a plurality of sequential segments each of which includes a register and an associated logic circuit. Each logic circuit includes a related memory.
The systolic array is used to compare long strings of digital data. In operation, a first string of digital data is "pumped" through the circuit by progressively transferring the string, section by section, from the first register, to the second and so forth. The first section of the string is loaded in parallel to the first register and thereafter, in sequence with conventional clocking circuitry, additional sections are loaded and advanced through each segment of the array. The first string of data is stored, in separate sections, in the memories associated with each logic circuit.
After the first data string is so stored, a second string is similarly "pumped" through the array. The logic circuitry in each segment performs logic operations on each section of data in the second string as it passes from segment to segment. The data output from the last segment in the array provides an indication of the similarity of the first and second strings of data.
In parallel testing of such an array, test vectors are applied to the device's input while the device performs as described above. The device's output is observed for correct behavior. Such testing suffers disadvantages relating to observability and controllability. In other words, it is difficult first, to control a logic circuit intermediate the first and last segments of the array and second, even if such control is exercised, it is difficult to observe the resultant data produced by such a logic circuit to see whether or not it performed as expected on the test vector.
One approach to overcoming the drawbacks associated with controllability and observability of testing as described above comprises designing the circuit so that each of the registers therein can be connected to form a single long shift register. Thereafter, a test vector having a length equal to the total number of memory elements in all of the registers is shifted sequentially through the shift register so formed. After the test vector is so loaded into the registers, each register is again converted to its normal latching operation. The array is then cycled to advance the data in each register through the logic circuit associated therewith and into the next register in the array. Thereafter the registers are again configured to form a single shift register and the data therein is sequentially shifted from the circuit. The resultant data is then examined, section by section, to determine whether or not each segment in the array performed as expected. The foregoing procedure is sometimes referred to in the art as serial scan testing.
When arrays have either a large number of segments or when the register in each segment includes a large number of memory elements, or both, problems arise in connection with serial scan testing. For example, in a systolic array there may be 16 segments, each having 150 memory elements. Serial scan testing such an array requires a test vector having 2400 (16.times.150) bits therein. Such a test vector exceeds the capacity of some testing equipment, makes debugging the circuit very difficult and makes generation of the test vector extremely complex.